Thursday, March 31, 2011


Microelectromechanical systems
Microelectromechanical systems (MEMS) (also written as micro-electro-mechanical, MicroElectroMechanical or microelectronic and microelectromechanical systems) is the technology of very small mechanical devices driven by electricity; it merges at the nano-scale into nanoelectromechanical systems (NEMS) and nanotechnology. MEMS are also referred to as micromachines (in Japan), or Micro Systems Technology - MST (in Europe).
MEMS are separate and distinct from the hypothetical vision of molecular nanotechnology or molecular electronics. MEMS are made up of components between 1 to 100 micrometres in size (i.e. 0.001 to 0.1 mm) and MEMS devices generally range in size from 20 micrometres (20 millionths of a metre) to a millimetre. They usually consist of a central unit that processes data, the microprocessor and several components that interact with the outside such as microsensors.[1] At these size scales, the standard constructs of classical physics are not always useful. Because of the large surface area to volume ratio of MEMS, surface effects such as electrostatics and wetting dominate volume effects such as inertia or thermal mass.
The potential of very small machines was appreciated before the technology existed that could make them—see, for example, Richard Feynman's famous 1959 lecture There's Plenty of Room at the Bottom. MEMS became practical once they could be fabricated using modified semiconductor device fabrication technologies, normally used to make electronics. These include molding and plating, wet etching (KOH, TMAH) and dry etching (RIE and DRIE), electro discharge machining (EDM), and other technologies capable of manufacturing small devices. An early example of a MEMS device is the resonistor – an electromechanical monolithic resonator.

MEMS description
MEMS technology can be implemented using a number of different materials and manufacturing techniques, depending on target device and market sector.
Materials for MEMS manufacturing
Silicon is the material used to create most integrated circuits used in consumer electronics in the modern world. The economies of scale, ready availability of cheap high-quality materials and ability to incorporate electronic functionality make silicon attractive for a wide variety of MEMS applications. Silicon also has significant advantages engendered through its material properties. In single crystal form, silicon is an almost perfect Hookean material, meaning that when it is flexed there is virtually no hysteresis and hence almost no energy dissipation. As well as making for highly repeatable motion, this also makes silicon very reliable as it suffers very little fatigue and can have service lifetimes in the range of billions to trillions of cycles without breaking. The basic techniques for producing all silicon based MEMS devices are deposition of material layers, patterning of these layers by photolithography and then etching to produce the required shapes.
Even though the electronics industry provides an economy of scale for the silicon industry, crystalline silicon is still a complex and relatively expensive material to produce. Polymers on the other hand can be produced in huge volumes, with a great variety of material characteristics. MEMS devices can be made from polymers by processes such as injection molding, embossing or stereolithography and are especially well suited to microfluidic applications such as disposable blood testing cartridges.
Metals can also be used to create MEMS elements. While metals do not have some of the advantages displayed by silicon in terms of mechanical properties, when used within their limitations, metals can exhibit very high degrees of reliability.
Metals can be deposited by electroplating, evaporation, and sputtering processes.
Commonly used metals include gold, nickel, aluminium, copper, chromium, titanium, tungsten, platinum, and silver.
MEMS basic processes
This chart is not complete  :

Basic Process




Deposition processes
One of the basic building blocks in MEMS processing is the ability to deposit thin films of material with a thickness anywhere between a few nanometres to about 100 micrometres.
Physical deposition
There are two types of physical deposition processes.
Physical vapor deposition (PVD)
Physical vapor deposition consists of a process in which a material is removed from a target, and deposited on a surface. Techniques to do this include the process of sputtering, in which an ion beam liberates atoms from a target, allowing them to move through the intervening space and deposit on the desired substrate, and Evaporation (deposition), in which a material is evaporated from a target using either heat (thermal evaporation) or an electron beam (e-beam evaporation) in a vacuum system.
Chemical deposition
Chemical deposition techniques include chemical vapor deposition ("CVD"), in which a stream of source gas reacts on the substrate to grow the material desired. This can be further divided into categories depending on the details of the technique, for example, LPCVD (Low Pressure chemical vapor deposition) and PECVD (Plasma Enhanced chemical vapor deposition).
Oxide films can also be grown by the technique of thermal oxidation, in which the (typically silicon) wafer is exposed to oxygen and/or steam, to grow a thin surface layer of silicon dioxide.
Patterning in MEMS is the transfer of a pattern into a material.
Lithography in MEMS context is typically the transfer of a pattern into a photosensitive material by selective exposure to a radiation source such as light. A photosensitive material is a material that experiences a change in its physical properties when exposed to a radiation source. If a photosensitive material is selectively exposed to radiation (e.g. by masking some of the radiation) the pattern of the radiation on the material is transferred to the material exposed, as the properties of the exposed and unexposed regions differs.
This exposed region can then be removed or treated providing a mask for the underlying substrate. Photolithography is typically used with metal or other thin film deposition, wet and dry etching.
KrF ArF Immersion EUV
Electron beam lithography
Electron beam lithography (often abbreviated as e-beam lithography) is the practice of scanning a beam of electrons in a patterned fashion across a surface covered with a film (called the resist),[4] ("exposing" the resist) and of selectively removing either exposed or non-exposed regions of the resist ("developing"). The purpose, as with photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate material, often by etching. It was developed for manufacturing integrated circuits, and is also used for creating nanotechnology architectures.
The primary advantage of electron beam lithography is that it is one of the ways to beat the diffraction limit of light and make features in the nanometer regime. This form of maskless lithography has found wide usage in photomask-making used in photolithography, low-volume production of semiconductor components, and research & development.
The key limitation of electron beam lithography is throughput, i.e., the very long time it takes to expose an entire silicon wafer or glass substrate. A long exposure time leaves the user vulnerable to beam drift or instability which may occur during the exposure. Also, the turn-around time for reworking or re-design is lengthened unnecessarily if the pattern is not being changed the second time.
It is known that focused-ion-beam lithography has the capability of writing extremely fine lines (less than 50 nm line and space has been achieved) without proximity effect. However, because the writing field in ion-beam lithography is quite small, largearea patterns must be created by stitching together the small fields.
X-ray lithography, is a process used in electronic industry to selectively remove parts of a thin film. It uses X-rays to transfer a geometric pattern from a mask to a light-sensitive chemical photoresist, or simply "resist," on the substrate. A series of chemical treatments then engraves the produced pattern into the material underneath the photoresist.
Etching processes
There are two basic categories of etching processes: wet etching and dry etching. In the former, the material is dissolved when immersed in a chemical solution. In the latter, the material is sputtered or dissolved using reactive ions or a vapor phase etchant.[5][6] for a somewhat dated overview of MEMS etching technologies.
Wet etching
Wet chemical etching consists in selective removal of material by dipping a substrate into a solution that dissolves it. The chemical nature of this etching process provides a good selectivity, which means the etching rate of the target material is considerably higher than the mask material if selected carefully.
Isotropic etching
Etching progresses at the same speed in all directions. Long and narrow holes in a mask will produce v-shaped grooves in the silicon. The surface of these grooves can be atomically smooth if the etch is carried out correctly, with dimensions and angles being extremely accurate.
Anisotropic etching
Some single crystal materials, such as silicon, will have different etching rates depending on the crystallographic orientation of the substrate. This is known as anisotropic etching and one of the most common examples is the etching of silicon in KOH (potassium hydroxide), where Si <111> planes etch approximately 100 times slower than other planes (crystallographic orientations). Therefore, etching a rectangular hole in a (100)-Si wafer results in a pyramid shaped etch pit with 54.7° walls, instead of a hole with curved sidewalls as with isotropic etching.
HF etching
Hydrofluoric acid is commonly used as an aqueous etchant for silicon dioxide (SiO2, also known as BOX for SOI), usually in 49% concentrated form, 5:1, 10:1 or 20:1 BOE (buffered oxide etchant) or BHF (Buffered HF). They were first used in medieval times for glass etching. It was used in IC fabrication for patterning the gate oxide until the process step was replaced by RIE.
Hydrofluoric acid is considered one of the more dangerous acids in the cleanroom. It penetrates the skin upon contact and it diffuses straight to the bone. Therefore the damage is not felt until it is too late.
Electrochemical etching
Electrochemical etching (ECE) for dopant-selective removal of silicon is a common method to automate and to selectively control etching. An active p-n diode junction is required, and either type of dopant can be the etch-resistant ("etch-stop") material. Boron is the most common etch-stop dopant. In combination with wet anisotropic etching as described above, ECE has been used successfully for controlling silicon diaphragm thickness in commercial piezoresistive silicon pressure sensors. Selectively doped regions can be created either by implantation, diffusion, or epitaxial deposition of silicon.
Dry etching
Vapor etching
Xenon difluoride etching
Xenon difluoride (XeF2) is a dry vapor phase isotropic etch for silicon originally applied for MEMS in 1995 at University of California, Los Angeles.[7][8] Primarily used for releasing metal and dielectric structures by undercutting silicon, XeF2 has the advantage of a stiction-free release unlike wet etchants. Its etch selectivity to silicon is very high, allowing it to work with photoresist, SiO2, silicon nitride, and various metals for masking. Its reaction to silicon is "plasmaless", is purely chemical and spontaneous and is often operated in pulsed mode. Models of the etching action are available,[9] and university laboratories and various commercial tools offer solutions using this approach.
Plasma etching
Reactive ion etching (RIE)
In reactive ion etching (RIE), the substrate is placed inside a reactor, and several gases are introduced. A plasma is struck in the gas mixture using an RF power source, which breaks the gas molecules into ions. The ions accelerate towards, and react with, the surface of the material being etched, forming another gaseous material. This is known as the chemical part of reactive ion etching. There is also a physical part, which is similar to the sputtering deposition process. If the ions have high enough energy, they can knock atoms out of the material to be etched without a chemical reaction. It is a very complex task to develop dry etch processes that balance chemical and physical etching, since there are many parameters to adjust. By changing the balance it is possible to influence the anisotropy of the etching, since the chemical part is isotropic and the physical part highly anisotropic the combination can form sidewalls that have shapes from rounded to vertical. RIE can be deep (Deep RIE or deep reactive ion etching (DRIE)).
Deep RIE (DRIE) is a special subclass of RIE that is growing in popularity. In this process, etch depths of hundreds of micrometres are achieved with almost vertical sidewalls. The primary technology is based on the so-called "Bosch process",[10] named after the German company Robert Bosch, which filed the original patent, where two different gas compositions alternate in the reactor. Currently there are two variations of the DRIE. The first variation consists of three distinct steps (the Bosch Process as used in the Plasma-Therm tool) while the second variation only consists of two steps (ASE used in the STS tool). In the 1st Variation, the etch cycle is as follows: (i) SF6 isotropic etch; (ii) C4F8 passivation; (iii) SF6 anisoptropic etch for floor cleaning. In the 2nd variation, steps (i) and (iii) are combined.
Both variations operate similarly. The C4F8 creates a polymer on the surface of the substrate, and the second gas composition (SF6 and O2) etches the substrate. The polymer is immediately sputtered away by the physical part of the etching, but only on the horizontal surfaces and not the sidewalls. Since the polymer only dissolves very slowly in the chemical part of the etching, it builds up on the sidewalls and protects them from etching. As a result, etching aspect ratios of 50 to 1 can be achieved. The process can easily be used to etch completely through a silicon substrate, and etch rates are 3–6 times higher than wet etching.
MEMS manufacturing technologies
Bulk micromachining
Bulk micromachining is the oldest paradigm of silicon based MEMS. The whole thickness of a silicon wafer is used for building the micro-mechanical structures.Silicon is machined using various etching processes. Anodic bonding of glass plates or additional silicon wafers is used for adding features in the third dimension and for hermetic encapsulation. Bulk micromachining has been essential in enabling high performance pressure sensors and accelerometers that have changed the shape of the sensor industry in the 80's and 90's.
Surface micromachining
Surface micromachining uses layers deposited on the surface of a substrate as the structural materials, rather than using the substrate itself.Surface micromachining was created in the late 1980s to render micromachining of silicon more compatible with planar integrated circuit technology, with the goal of combining MEMS and integrated circuits on the same silicon wafer. The original surface micromachining concept was based on thin polycrystalline silicon layers patterned as movable mechanical structures and released by sacrificial etching of the underlying oxide layer. Interdigital comb electrodes were used to produce in-plane forces and to detect in-plane movement capacitively. This MEMS paradigm has enabled the manufacturing of low cost accelerometers for e.g. automotive air-bag systems and other applications where low performance and/or high g-ranges are sufficient. Analog Devices have pioneered the industrialization of surface micromachining and have realized the co-integration of MEMS and integrated circuits.
High aspect ratio (HAR) silicon micromachining
Both bulk and surface silicon micromachining are used in the industrial production of sensors, ink-jet nozzles, and other devices. But in many cases the distinction between these two has diminished. A new etching technology, deep reactive-ion etching, has made it possible to combine good performance typical of bulk micromachining with comb structures and in-plane operation typical of surface micromachining. While it is common in surface micromachining to have structural layer thickness in the range of 2 µm, in HAR silicon micromachining the thickness can be from 10 to 100 µm. The materials commonly used in HAR silicon micromachining are thick polycrystalline silicon, known as epi-poly, and bonded silicon-on-insulator (SOI) wafers although processes for bulk silicon wafer also have been created (SCREAM). Bonding a second wafer by glass frit bonding, anodic bonding or alloy bonding is used to protect the MEMS structures. Integrated circuits are typically not combined with HAR silicon micromachining. The consensus of the industry at the moment seems to be that the flexibility and reduced process complexity obtained by having the two functions separated far outweighs the small penalty in packaging. A comparison of different high-aspect-ratio microstructure technologies can be found in the HARMST article.
A forgotten history regarding surface micromachining revolved around the choice of polysilicon A or B. Fine grained (<300A grain size, US4897360), post strain annealed pure polysilicon was advocated by Prof Henry Guckel (U. Wisconsin); while a larger grain, doped stress controlled polysilicon was advocated by the UC Berkeley group.
microelectromechanical systems chip, sometimes called "lab on a chip"
In one viewpoint MEMS application is categorized by type of use.
Companies with strong MEMS programs come in many sizes. The larger firms specialize in manufacturing high volume inexpensive components or packaged solutions for end markets such as automobiles, biomedical, and electronics. The successful small firms provide value in innovative solutions and absorb the expense of custom fabrication with high sales margins. In addition, both large and small companies work in R&D to explore MEMS technology.
Industry structure
The global market for micro-electromechanical systems, which includes products such as automobile airbag systems, display systems and inkjet cartridges totaled $40 billion in 2006 according to Global MEMS/Microsystems Markets and Opportunities, a research report from SEMI and Yole Developpement and is forecasted to reach $72 billion by 2011.[14]
MEMS devices are defined as die-level components of first-level packaging, and include pressure sensors, accelerometers, gyroscopes, microphones, digital mirror displays, micro fluidic devices, etc. The materials and equipment used to manufacture MEMS devices topped $1 billion worldwide in 2006. Materials demand is driven by substrates, making up over 70 percent of the market, packaging coatings and increasing use of chemical mechanical planarization (CMP). While MEMS manufacturing continues to be dominated by used semiconductor equipment, there is a migration to 200 mm lines and select new tools, including etch and bonding for certain MEMS applications.

Tuesday, January 4, 2011

Minimization of Boolean expressions using Karnaugh maps

Given the following truth table for the majority function.

The Boolean algebraic expression is
m = a'bc + ab'c + abc' + abc.
We have seen that the minimization is done as follows.
m = a'bc + abc + ab'c + abc + abc' + abc
= (a' + a)bc + a(b' + b)c + ab(c' + c)
= bc + ac + ab
The abc term was replicated and combined with the other terms.
To use a Karnaugh map we draw the following map which has a position (square) corresponding to each of the 8 possible combinations of the 3 Boolean variables. The upper left position corresponds to the 000 row of the truth table, the lower right position corresponds to 110. Each square has two coordinates, the vertical coordinate corresponds to the value of variable a and the horizontal corresponds to the values of b and c.

The 1s are in the same places as they were in the original truth table. The 1 in the first row is at position 011 (a = 0, b = 1, c = 1). The vertical coordinate, variable a, has the value 0. The horizontal coordinates, the variables b and c, have the values 1 and 1.
The minimization is done by drawing circles around sets of adjacent 1s. Adjacency is horizontal, vertical, or both. The circles must always contain 2n 1s where n is an integer.

We have circled two 1s. The fact that the circle spans the two possible values of a (0 and 1) means that the a term is eliminated from the Boolean expression corresponding to this circle. The bracketing lines shown above correspond to the positions on the map for which the given variable has the value 1. The bracket delimits the set of squares for which the variable has the value 1. We see that the two circled 1s are at the intersection of sets b and c, this means that the Boolean expression for this set is bc.

Now we have drawn circles around all the 1s. The left bottom circle is the term ac. Note that the circle spans the two possible values of b, thus eliminating the b term. Another way to think of it is that the set of squares in the circle contains the same squares as the set a intersected with the set c. The other circle (lower right) corresponds to the term ab. Thus the expression reduces to
bc + ac + ab
as we saw before.
What is happening? What does adjacency and grouping the 1s together have to do with minimization? Notice that the 1 at position 111 was used by all 3 circles. This 1 corresponds to the abc term that was replicated in the original algebraic minimization. Adjacency of 2 1s means that the terms corresponding to those 1s differ in one variable only. In one case that variable is negated and in the other it is not.
For example, in the first map above, the one with only 1 circle. The upper 1 is the term a'bc and the lower is abc. Obviously they combine to form bc ( a'bc + abc = (a' + a)bc = bc ). That is exactly what we got using the map.
The map is easier than algebraic minimization because we just have to recognize patterns of 1s in the map instead of using the algebraic manipulations. Adjacency also applies to the edges of the map.
Let's try another 3 variable map.

At first it may seem that we have two sets, one on the left of the map and the other on the right. Actually there is only 1 set because the left and right are adjacent as are the top and bottom. The expression for all 4 1s is c'. Notice that the 4 1s span both values of a (0 and 1) and both values of b (0 and 1). Thus, only the c value is left. The variable c is 0 for all the 1s, thus we have c'. The other way to look at it is that the 1's overlap the horizontal b line and the short vertical a line, but they all lay outside the horizontal c line, so they correspond to c'. (The horizontal c line delimits the c set. The c' set consists of all squares outside the c set. Since the circle includes all the squares in c', they are defined by c'. Again, notice that both values of a and b are spanned, thus eliminating those terms.)

Now for 4 Boolean variables. The Karnaugh map is drawn as shown below.

The following corresponds to the Boolean expression
q = a'bc'd + a'bcd + abc'd' + abc'd + abcd + abcd' + ab'cd + ab'cd'

RULE: Minimization is achieved by drawing the smallest possible number of circles, each containing the largest possible number of 1s.
Grouping the 1s together results in the following.

The expression for the groupings above is
q = bd + ac + ab
This expression requires 3 2-input and gates and 1 3-input or gate.
We could have accounted for all the 1s in the map as shown below, but that results in a more complex expression requiring a more complex gate.

The expression for the above is bd + ac + abc'd'. This requires 2 2-input and gates, a 4-input and gate, and a 3 input or gate. Thus, one of the and gates is more complex (has two additional inputs) than required above. Two inverters are also needed.
Don't Cares
Sometimes we do not care whether a 1 or 0 occurs for a certain set of inputs. It may be that those inputs will never occur so it makes no difference what the output is. For example, we might have a bcd (binary coded decimal) code which consists of 4 bits to encode the digits 0 (0000) through 9 (1001). The remaining codes (1010 through 1111) are not used. If we had a truth table for the prime numbers 0 through 9, it would be

The ds in the above stand for "don't care", we don't care whether a 1 or 0 is the value for that combination of inputs because (in this case) the inputs will never occur.

The circle made entirely of 1s corresponds to the expression a'd and the combined 1 and d circle (actually a combination of arcs) is b'c. Thus, if the disallowed input 1011 did occur, the output would be 1 but if the disallowed input 1100 occurs, its output would be 0. The minimized expression is
p = a'd + b'c
Notice that if we had ignored the ds and only made a circle around the 2 1s, the resulting expression would have been more complex, a'b'c instead of b'c.

Thursday, December 23, 2010

Logic Gates and boolean algebra

Digital Logic Circuit

Boolean algebra
                         Binary logic was first proposed by 19th-century British logician and mathematician George Boole, who in 1847 invented a two-valued system of algebra that represented logical relationships and operations. This system of algebra, called Boolean Algebra, was used by German engineer Konrad Zuse in the 1930s for his Z1 calculating machine. It was also used in the design of the first digital computer in the late 1930s by American physicist John Atanasoff and his graduate student Clifford Berry. During 1944 and 1945 Hungarian-born American mathematician John von Neumann suggested using the binary arithmetic system for storing programs in computers. In the 1930s and 1940s British mathematician Alan Turing and American mathematician Claude Shannon also recognized how binary logic was well suited to the development of digital computers.
Functions performed by logic circuits
"True" can be represented by a 1 and "false" by a 0, and in logic circuits the numerals appear as signals of two different voltages. Logic circuits are used to make specific true-false decisions based on the presence of multiple true-false signals at the inputs. The signals may be generated by mechanical switches or by solid-state transducers. Once the input signal has been accepted and conditioned (to remove unwanted electrical signals, or "noise"), it is processed by the digital logic circuits. The various families of digital logic devices, usually integrated circuits, perform a variety of logic functions through logic gates, including "OR,""AND," and "NOT," and combinations of these (such as "NOR," which includes both OR and NOT)
Types of Logic Components
One widely used logic family is the transistor-transistor logic (TTL). Another family is the complementary metal oxide semiconductor logic (CMOS), which performs similar functions at very low power levels but at slightly lower operating speeds. Several other, less popular families of logic circuits exist, including the currently obsolete resistor-transistor logic (RTL) and the emitter coupled logic (ELC), the latter used for very-high-speed systems.
Logical Gates
The elemental blocks in a logic device are called digital logic gates.
An AND gate has two or more inputs and a single output. The output of an AND gate is true only if all the inputs are true.
An OR gate has two or more inputs and a single output. The output of an OR gate is true if any one of the inputs is true and is false if all of the inputs are false.
An INVERTER has a single input and a single output terminal and can change a true signal to a false signal, thus performing the NOT function.
An NAND gate has two or more inputs and a single output. The output of an NAND gate is true if any one of the inputs is false and is false if all the inputs are true.
An NOR gate has two or more inputs and a single output. The output of an NOR gate is true if all the inputs are false and is false if the inputs are different.
An EXCLUSIVE OR gate has two or more inputs and a single output. The output of an EXCLUSIVE OR gate is true if the inputs are different and is  false if the inputs are the same.
Obs. You can easily observe how the NAND gate can be emulated by two other gates (AND , NOT). The output of the AND gate is connected to the input of the NOT gate.
The output of the NAND gate is true if the one of the input is false. Now let's verify: We put true and false on the inputs of the AND gate. This gate now returns false answer (0).This false answer is the input of the NOT gate. This gate returns true (opposite of false). You can now see that the answer is similar to the one witch NAND returned.
Other facts
To perform a desired overall function, large numbers of logic elements may be connected in complex circuits. In some cases microprocessors are utilized to perform many of the switching and timing functions of the individual logic elements. The processors are specifically programmed with individual instructions to perform a given task or tasks. An advantage of microprocessors is that they make possible the performance of different logic functions, depending on the program instructions that are stored. A disadvantage of microprocessors is that normally they operate in a sequential mode, which may be too slow for some applications. In these cases specifically designed logic circuits are used.

Control Process-Block Diagram

Transfer Functions
The relationship from an input signal, u, to an output signal, y, in the Laplace transform domain.
  1. Equation form: L[y] = G(s) L[u]
  2. Block Diagram form:

Block Diagram Equivalence:
  1. Series:
      is equivalent to  
  3. Parallel:
      is equivalent to:  
  5. Positive Feedback:
      is equivalent to:  
  7. Negative Feedback:

is equivalent to

Additional Rules:
  1. Summing Junctions
  3. For the transfer functions of multiple inputs: u1, u2, etc., to output y, use superposition. That is, for the transfer function of u1 to y, disregard the effects u2, u3 etc.

Example 1:


is equivalent to: